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PRELIMINARY PRODUCT INFORMATION
PD780016Y, 780018Y
8-BIT SINGLE-CHIP MICROCONTROLLER
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD780016Y and 780018Y are members of the PD780018Y subseries of the 78K/0 series microcontrollers. Besides a high-speed, high-performance CPU, these microcontrollers have on-chip ROM, RAM, I/O ports, timer, serial interface, real-time output port, interrupt control, and various other peripheral hardware. The PD78P0018Y devices including a one-time PROM version and an EPROM version, both of which can operate in the same power supply voltage range as a mask ROM version, and various development tools are available. The details of the functions are described in the following user's manuals. Be sure to read it before starting design.
PD780018,780018Y Subseries User's Manual: U11754E 78K/0 Series User's Manual - Instructions : IEU-1372
FEATURES * Internal high capacity ROM and RAM
Item Part Number Program Memory (ROM) 48K bytes 60K bytes Data Memory Internal High-Speed RAM 1024 bytes Buffer RAM Internal Extended RAM 1024 bytes Package
PD780016Y PD780018Y
32 bytes
100-pin plastic QFP (14 x 20 mm)
* External memory expansion space: 64K bytes * Instruction execution time can be changed from high-speed (0.4 s) to ultra-low-speed (122 s) * I/O ports: 88
* Serial interface: 3 channels
* 3-wire serial I/O mode (with automatic data transmit/receive function): 1 channel * 3-wire serial I/O mode (with time division transfer function): 1 channel * I2C bus mode (supporting multi-task): 1 channel * Supply voltage : VDD = 2.7 to 5.5 V
* 8-bit resolution A/D converter: 8 channels * Timer: 7 channels
APPLICATION FIELD
Cellular phones, cordless phones, AV equipment, etc.
The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Document No. U11810EJ1V0PM00 (1st edition) Date Published December 1996 N Printed in Japan
(c)
1996
PD780016Y, 780018Y
ORDERING INFORMATION
Part Number Package 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm)
PD780016YGF-XXX-3BA PD780018YGF-XXX-3BA
Remark XXX indicates ROM code suffix.
78K/0 SERIES DEVELOPMENT
These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are subseries names.
Under mass production Under development Y subseries supports I2C bus. For control 100-pin 100-pin 100-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD78078 PD78070A PD780018Note PD78058F PD78054 PD780034 PD780024 PD780964 PD780924 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083
For driving FIPTM
PD78078Y PD78070AY PD780018YNote PD78058FY PD78054Y PD780034Y PD780024Y
Timer added to the PD78054, external interface functions enhanced ROM-less product for the PD78078 Enhanced serial I/O of the PD78078, functions limited Reduced EMI noise product of the PD78054 UART and D/A added to the PD78014, enhanced I/O Enhanced A/D of the PD780024 Enhanced serial I/O of the PD78018F. Reduced EMI noise product. Enhanced A/D of the PD780924 Internal inverter control circuit and UART. Reduced EMI noise product. Reduced EMI noise of the PD78018F. Low-voltage (1.8 V) operation product of the PD78014, ROM, RAM variations enhanced A/D, 16-bit timer added to the PD78002 A/D added to the PD78002 Basic subseries for control Internal UART, low-voltage (1.8 V) operation possible
PD78018FY PD78014Y PD78002Y
78K/0 series
100-pin 80-pin 64-pin
PD780208 PD78044F PD78024
I/O, FIP C/D of the PD78044F enhanced, display output total: 53 6-bit U/D counter added to the PD78024, display output total: 34 Basic subseries for FIP driving, display output total: 26
For driving LCD 100-pin 100-pin 100-pin
PD780308 PD78064B PD78064
Supporting IEBusTM
PD780308Y PD78064Y
Enhanced SIO of the PD78064, ROM, RAM extended Reduced EMI noise product of the PD78064 Basic subseries for LCD driving, internal UART
80-pin
PD78098
For LV
IEBus controller added to the PD78054
64-pin
PD78P0914
PWM output, internal LV digital code decoder, Hsync counter
Note Under planning
2
PD780016Y, 780018Y
The major functional differences among the subseries are shown below.
Function Subseries Name For Control PD78078 ROM Capacity Timer 8-bit 16-bit Watch WDT 1ch 1ch 1ch 8-bit 10-bit 8-bit A/D A/D D/A 8ch -- 2ch Serial Interface 3ch (UART: 1ch) VDD External MIN. Eexpansion Value 1.8 V 2.7 V
I/O
32 K-60 K 4ch --
88 61
PD78070A PD78058F PD78054 PD780024 PD780964 PD780924 PD78014H
PD780018 48 K-60 K
2ch 16 K-60 K -- 8ch 3ch Note -- -- 8ch 2ch 1ch 1ch 8ch -- 8ch --
-- 2ch
2ch 3ch (UART: 1ch)
88 69 2.0 V
PD780034 8 K-32 K
--
51
1.8 V
2ch (UART: 2ch)
47
2.7 V
2ch
53
1.8 V
PD78018F 8 K-60 K PD78014 PD78002 PD78083
For FIP driving 8 K-32 K -- -- 1ch -- 1ch 1ch 1ch -- 8ch 8ch -- -- 1ch (UART: 1ch) 2ch 1ch 39 53 33 74 68 54 1ch 1ch 1ch 8ch -- -- 3ch (UART: 1ch) 2ch (UART: 1ch) 57 1.8 V 2.0 V -- 1.8 V 2.7 V -- -- 2.7 V --
PD780001 8 K
8 K-16 K
PD780208 32 K-60 K 2ch PD78044F 16 K-40 K PD78024
24 K-32 K
For LCD driving
PD780308 48 K-60 K 2ch PD78064B 32 K PD78064
16 K-32 K 32 K-60 K 2ch 6ch
For IEBus For LV
PD78098
1ch --
1ch --
1ch 1ch
8ch 8ch
-- --
2ch --
3ch (UART: 1ch) 2ch
69 54
2.7 V 4.5 V
PD78P0914 32 K
Note
10-bit timer: 1 channel
3
PD780016Y, 780018Y
OVERVIEW OF FUNCTION
Part Number Item Internal memory ROM Internal high-speed RAM Buffer RAM Internal expansion RAM Memory space General registers Instruction cycle When main system clock selected When subsystem clock selected Instruction set 48K bytes 1024 bytes 32 butes 1024 bytes 64K bytes 8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip instruction execution time selective function 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (at 5.0 MHz) 122 s (at 32.768 kHz) * * * * 16-bit operation Multiplcation/division (8 bits x 8 bits,16 bits / 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD adjustment, etc. Total * CMOS input * CMOS I/O A/D converter Serial interface : 88 :9 : 79 60K bytes
PD780016Y
PD780018Y
I/O ports
* 8-bit resolution x 8 channels * 3-wire serial I/O mode (with automatic data transmit/receive function): 1 channel * 3-wire serial I/O mode (with time division transfer function) : 1 channel * I2C bus mode (supporting multi-task) : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 4 1 1 channel channels channel channel
Timer
Timer output Clock output
5 (14-bit PWM output x 1, 8-bit PWM output x 2) 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (at main system clock of 5.0 MHz) 32.768 kHz (at subsystem clock of 32.768 kHz) 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock: at 5.0 MHz) Internal : 12 External : 7 Internal : 1 1 Internal : 1 External : 1 VDD = 2.7 to 5.5 V * 100-pin plastic QFP (14 x 20 mm)
Buzzer output Vectored interrupt sources Maskable
Non-maskable Software
Test input
Supply voltage Package
4
PD780016Y, 780018Y
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 6 2. BLOCK DIAGRAM .............................................................................................................................. 8 3. PIN FUNCTIONS ................................................................................................................................. 9
3.1 3.2 3.3 Port Pins ...................................................................................................................................................... 9 Non-port Pins ............................................................................................................................................ 11 Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 13
4. MEMORY SPACE .............................................................................................................................. 16 5. PERIPHERAL HARDWARE FUNCTIONS ....................................................................................... 17
5.1 5.2 5.3 5.4 5.5 5.6 5.7 Ports ........................................................................................................................................................... 17 Clock Generator ........................................................................................................................................ 18 Timer/Event Counter ................................................................................................................................ 18 Clock Output Control Circuit .................................................................................................................. 22 Buzzer Output Control Circuit ................................................................................................................ 22 A/D Converter ........................................................................................................................................... 23 Serial Interfaces ........................................................................................................................................ 24
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS ....................................................................... 26
6.1 6.2 Interrupt Functions .................................................................................................................................. 26 Test Functions .......................................................................................................................................... 29
7. EXTERNAL DEVICE EXPANSION FUNCTIONS ............................................................................. 30 8. STANDBY FUNCTION ...................................................................................................................... 30 9. RESET FUNCTION ............................................................................................................................ 31 10. INSTRUCTION SET ........................................................................................................................... 32 11. PACKAGE DRAWINGS ..................................................................................................................... 34 APPENDIX A. DEVELOPMENT TOOLS................................................................................................ 35 APPENDIX B. RELATED DOCUMENTS ............................................................................................... 37
5
PD780016Y, 780018Y
1. PIN CONFIGURATION (TOP VIEW)
* 100-pin plastic QFP (14 x 20 mm)
PD780016YGF-XXX-3BA, 780018YGF-XXX-3BA
P156 P155 P154 P153 P152 P151 P150 P37 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P103 P102 P101/TI6/TO6 P100/TI5/TO5 P67/ASTB
P80/A0 P81/A1 P82/A2 P83/A3 P84/A4 P85/A5 P86/A6 P87/A7 IC X2 X1 VDD1 XT2 XT1 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 VDD0 AVREF P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P66/WAIT P65/WR P64/RD P63 P62 P61 P60 P57/A15 P56/A14 VSS0 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P117/SCL P116/SDA P115 P114 P113 P112/SCK4C
Cautions 1. Connect IC (internally connected) pin directly to VSS0. 2. AVSS pin should be connected to VSS0. Remark When the circuit is used in an application where the noise generated from the inside of the microcontroller needs to be reduced, take countermeasures against noise such as supplying power to VDD0 and VDD1 separately and connecting VSS0 and VSS1 to the ground line separately.
6
P16/ANI6 P17/ANI7 AVSS P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25 VSS1 P26 P27 P90/SI4A P91/SO4A P92/SCK4A P93/SI4B P94/SO4B P95/SCK4B P110/SI4C P111/SO4C
PD780016Y, 780018Y
A0-A15 AD0-AD7 ANI0-ANI7 ASTB AVREF AVSS BUSY BUZ IC INTP0-INTP6 P00-P06 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P80-P87 P90-P96 P100-P103 P110-P117 P150-P156 : Address Bus : Address/Data Bus : Analog Input : Address Strobe : Analog Reference Voltage : Analog Ground : Busy : Buzzer Clock : Internally Connected : Interrupt from Peripherals : Port0 : Port1 : Port2 : Port3 : Port4 : Port5 : Port6 : Port8 : Port9 : Port10 : Port11 : Port15 PCL RD RESET SCK1 SCL SDA SI1 SI4A, SI4B, SI4C SO1 SO4A, SO4B, SO4C STB TI00, TI01 TI1, TI2, TI5, TI6 TO0-TO2, TO5, TO6 VDD0, VDD1 VSS0, VSS1 WAIT WR X1, X2 XT, XT2 : Programmable Clock : Read Strobe : Reset : Serial Clock : Serial Clock : Serial Data : Serial Input : Serial Input : Serial Output : Serial Output : Strobe : Timer Input : Timer Input : Timer Output : Power Supply : Ground : Wait : Write Strobe : Crystal (Main System Clock) : Crystal (Subsystem Clock)
SCK4A, SCK4B, SCK4C : Serial Clock
7
PD780016Y, 780018Y
2. BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit timer/ event counter 8-bit timer/ event counter 1 8-bit timer/ event counter 2 8-bit timer/ event counter 5 8-bit timer/ event counter 6 Watchdog timer Watch timer 78K/0 CPU Core
Port 0
P00 P01_P06
Port 1
P10_P17 P20_P27 P30_P37 P40_P47 P50_P57 P60_P67
Port 2
Port 3
TI5/TO5/P100
Port 4
TI6/TO6/P101
Port 5
Port 6
ROM
Port 8
P80_P87 P90_P95 P100_P103 P110_P117 P150_P156 AD0/P40_ AD7/P47 A0/P80_
SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI4A/P90 SO4A/P91 SCK4A/P92 SI4B/P93 SO4B/P94 SCK4B/P95 SI4C/P110 SO4C/P111 SCK4C/P112 SDA/P116 SCL/P117 ANI0/P10_ ANI7/P17 AVSS AVREF INTP0/P00_ INTP6/P06
Serial interface 1
Port 9
Port 10 Port 11 Serial interface 4
RAM
Port 15
Serial interface 5 External access A/D converter
A7/P87 A8/P50_ A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET
Interrupt control System control
X1 X2 XT1 XT2
BUZ/P36
Buzzer output
PCL/P35
Clock output control
VDD0, VDD1
VSS0, VSS1
IC
Remark The internal ROM capacity depends on the product.
8
PD780016Y, 780018Y
3. PIN FUNCTIONS 3.1 Port Pins (1/2)
After Reset Input Alternate Function Pin INTP0/TI00 INTP1/TI01 INTP2 INTP3 Input INTP4 INTP5 INTP6 Input Port 1 8-bit input port On-chip pull-up resistor can be used by software.Note P20 P21 P22 P23 P24 P25-P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47 Input/ output Port 4 8-bit input/output port Input/output can be specified in 8-bit units. When used as an input port, on-chip pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection. Input Input/ output Port 3 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input/ output Port 2 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input ANI0 to ANI7 SI1 SO1 SCK1 Input STB BUSY -- TO0 TO1 TO2 TI1 TI2 PCL BUZ --
Pin Name P00 P01 P02 P03 P04 P05 P06 P10 to P17
I/O Input Input/ output Port 0 7-bit I/O port Input only
Function
Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software.
Input
AD0 to AD7
Note
When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, on-chip pull-up resistor is automatically disconnected.
9
PD780016Y, 780018Y
3.1 Port Pins (2/2)
After Reset Input Alternate Function Pin A8 to A15
Pin Name P50 to P57
I/O Input/ output
Function Port 5 8-bit input/output port LED can be driven directly. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 6 8-bit input/ output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software.
P60 P61 P62 P63 P64 P65 P66 P67 P80 to P87
Input/ output
Input
--
RD WR WAIT ASTB Input/ output Port 8 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input A0 to A7
P90 P91 P92 P93 P94 P95 P100 P101 P102, P103 P110 P111 P112 P113-P115 P116 P117 P150-P156
Input/ output
Port 9 6-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software.
Input
SI4A SO4A SCK4A SI4B SO4B SCK4B
Input/ output
Port 10 4-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 11 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software.
Input
TI5/TO5 TI6/TO6 --
Input/ output
Input
SI4C SO4C SCK4C -- SDA SCL
Input/ output
Port 15 7-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software.
Input
--
10
PD780016Y, 780018Y
3.2 Non-port Pins (1/2)
After Reset Input Alternate Function Pin P00/TI00 P01/TI01 P02 P03 P04 P05 P06 Input Serial interface serial data input. Input P20 P90 P93 P110 Output Serial interface serial data output. Input P21 P91 P94 P111 Input/output Input /output Input/output of serial data of serial interface. Serial interface serial clock input/output. Input Input P116 P22 P92 P95 P112 P117 Output Input Input Serial interface automatic transmit/receive strobe output. Serial interface automatic transmit/receive busy input. External count clock input to 16-bit timer (TM0). Capture trigger signal input to capture register (CR00). External count clock input to 8-bit timer (TM1). External count clock input to 8-bit timer (TM2). External count clock input to 8-bit timer (TM5). External count clock input to 8-bit timer (TM6). Output 16-bit timer (TM0) output (also used for 14-bit PWM output). 8-bit timer (TM1) output. 8-bit timer (TM2) output. 8-bit timer (TM5) output (also used for 8-bit PWM output). 8-bit timer (TM6) output (also used for 8-bit PWM output). Output Output Input /output Clock output (for main system clock, subsystem clock trimming). Buzzer output. Low-order address/data bus at external memory expansion. Input Input Input Input Input Input Input P23 P24 P00/INTP0 P01/INTP1 P33 P34 P100/TO5 P100/TO6 P30 P31 P32 P100/TI5 P101/TI6 P35 P36 P40 to P47
Pin Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 SI1 SI4A SI4B SI4C SO1 SO4A SO4B SO4C SDA SCK1 SCK4A SCK4B SCK4C SCL STB BUSY TI00 TI01 TI1 TI2 TI5 TI6 TO0 TO1 TO2 TO5 TO6 PCL BUZ AD0 to AD7
I/O Input
Function External interrupt request input by which the active edge (rising edge, falling edge, or both rising and falling edges) can be specified.
11
PD780016Y, 780018Y
3.2 Non-port Pins (2/2)
After Reset Input Input Input P65 Input Input Input -- -- -- -- -- Subsystem clock oscillation crystal connection. Input -- Port block positive power supply. Port block ground potential. Positive power supply (except for port and analog blocks) Ground potential (except for port and analog blocks) Internal connection. Connect directly to VSS0. -- -- -- -- -- P66 P67 Alternate Function Pin P80 to P87 P50 to P57 P64
Pin Name A0 to A7 A8 to A15 RD WR WAIT ASTB
I/O Output Output Output
Function Low-order address bus at external memory expansion. High-order address bus at external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output.
Input Output
Wait insertion at external memory access. Strobe output which externally latches the address information output to ports 4, 5 and 8 to access external memory.
ANI0 to ANI7 AVREF AVSS RESET X1 X2 XT1 XT2 VDD0 VSS0 VDD1 VSS1 IC
Input Input -- Input Input -- Input -- -- -- -- -- --
A/D converter analog input. A/D converter reference voltage input (shared with analog power supply). A/D converter ground potential. Same potential as VSS0. System reset input. Main system clock oscillation crystal connection.
P10 to P17 -- -- -- -- -- -- -- -- -- -- -- --
12
PD780016Y, 780018Y
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, see Figure 3-1. Table 3-1. Types of Pin Input/Output Circuits (1/2)
Pin Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 P10/ANI0-P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25-P27 P30/TO0-P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P40/AD0-P47/AD7 P50/A8-P57/A15 P60-P63 P64/RD P65/WR P66/WAIT P67/ASTB P80/A0-P87/A7 P90/SI4A P91/SO4A P92/SCK4A P93/SI4B P94/SO4B P95/SCK4B
Input/Output Circuit Type 2 8-C
I/O Input Input/output
Recommended Connection for Unused Pins Connect to VSS0. Connect to VSS0 via a resistor individually.
9-B 8-C 5-H 8-C 5-H 8-C 5-H
Input Input/output
Connect to VDD0 or VSS0 via a resistor individually.
8-C
5-H
5-N 5-H
Input/output Input/output
Connect to VDD0 via a resistor individually. Connect to VDD0 or VSS0 via a resistor individually.
8-C 5-H 8-C
5-H 8-C
13
PD780016Y, 780018Y
Table 3-1. Types of Pin Input/Output Circuits (2/2)
Input/Output Circuit Type 8-C
Pin Name P100/TI5/TO5 P101/TI6/TO6 P102, P103 P110/SI4C P111/SO4C P112/SCK4C P113-P115 P116/SDA P117/SCL P150-P156 RESET XT1 XT2 AVREF AVSS IC
I/O Input/output
Recommended Connection for Unused Pins Connect to VDD0 or VSS0 via a resistor individually.
5-H 8-C 5-H 8-C 5-H 10-B
5-H 2 16 Input -- Connect to VDD0. Leave open. -- Connect to VSS0. --
Connect to VSS0.
14
PD780016Y, 780018Y
Figure 3-1. Pin Input/Output Circuits
Type 2
Type 9-B VDD0
IN IN
P-ch P-ch N-ch VSS0 VREF
pullup enable comparator
+ _
Schmitt-triggered input with hysteresis characteristic
threshold voltage input enable
Type 5-H pullup enable VDD0 data
VDD0
Type 10-B
VDD0
P-ch
pullup enable VDD0 data IN/OUT P-ch
P-ch
P-ch
IN/OUT open drain output disable N-ch VSS0
output disable
N-ch VSS0
input enable Type 5-N VDD0 Type 16
pullup enable VDD0
P-ch
feedback cut-off P-ch
data
P-ch IN/OUT
output disable
N-ch VSS0 XT1 XT2
Type 8-C
VDD0
pullup enable VDD0 data P-ch
P-ch
IN/OUT output disable N-ch VSS0
15
PD780016Y, 780018Y
4. MEMORY SPACE
The memory map of the PD780016Y and 780018Y is shown in Figure 4-1. Figure 4-1. Memory Map
FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH
General-purpose registers 32 x 8 bits
Internal high-speed RAM 1024 x 8 bits FB00H FAFFH Use prohibited FAE0H Data memory space FADFH FAC0H FABFH Use prohibited F800H F7FFH Internal extended RAM F400H F3FFH Program nnnnH+1 memory nnnnH space 1024 x 8 bits Use prohibited Note 1 CALLF entry area 0800H 07FFH nnnnH Buffer RAM 32 x 8 bits Program area 1000H 0FFFH
Program area
0080H 007FH CALLT table area 0040H 003FH Vector table area
Internal ROM Note 2
0000H
0000H
Notes 1. If external device expansion functions are to be employed for the PD780018Y, set the size of the internal ROM to below 56K bytes using the memory size switching register (IMS). 2. The internal ROM capacity depends on the product. (See the following table.)
Internal ROM Last Address nnnnH BFFFH EFFFH
Part Number
PD780016Y PD780018Y
16
PD780016Y, 780018Y
5. PERIPHERAL HARDWARE FUNCTIONS 5.1 Ports
Input/output ports are classified into two types. * CMOS input (P00, Port 1) * CMOS input/output (P01 to P06, Port 2 to 6, Port 8 to 11, Port 15) Total Table 5-1. Functions of Ports
Port Name Port 0 Pin Name P00 P01 to P06 Input only. Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input only. On-chip pull-up resistor can be used by software. Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input/output port. Input/output can be specified in 8-bit units. When used as an input port, on-chip pull-up resistor can be used by software. The test input flag (KRIF) is set to 1 by falling edge detection. Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. LED can be driven directly. Port 6 P60 to P67 Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 10 P100 to P103 Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Function
:9 : 79 : 88
Port 1
P10 to P17
Port 2
P20 to P27
Port 3
P30 to P37
Port 4
P40 to P47
Port 5
P50 to P57
Port 8
P80 to P87
Port 9
P90 to P95
Port 11
P110 to P117
Port 15
P150 to P156
17
PD780016Y, 780018Y
5.2 Clock Generator
There are two kinds of clock generators: main system and subsystem clock generators. It is possible to change the instruction execution time. * 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (at main system clock frequency of 5.0 MHz) * 122 s (at subsystem clock frequency of 32.768 kHz) Figure 5-1. Clock Generator Block Diagram
XT1 XT2
Subsystem clock oscillator
fXT
Watch timer, Clock output function Prescaler
X1 X2
Main system fX clock oscillator
Selector
fXX fXX 2
Prescaler
1 2
Division circuit
Clock to peripheral hardware
fX 2
fXX 22
fXX 23
fXX 24
fXT 2
STOP
Selector
MCSNote Oscillation mode select register
Standby control circuit
Wait control circuit
CPU clock (fCPU)
To INTP0 sampling clock
Note
Be sure to set 1 to MCS.
5.3 Timer/Event Counter
There are the following seven timer/event counter channels: * 16-bit timer/event counter * 8-bit timer/event counter * Watch timer * Watchdog timer : 1 channel : 4 channels : 1 channel : 1 channel Table 5-2. Types and Functions of Timer/Event Counters
16-bit Timer/Event 8-bit Timer/Event Counter Counters 1, 2 Interval timer Type External event counter Timer output PWM output Function Pulse width measurement Square wave output One-shot pulse output Interrupt request Test input 1 channel 1 output 1 output 2 inputs 1 output 1 output 2 -- 2 channels 2 outputs -- -- 2 outputs -- 2 -- 2 channels 2 outputs 2 outputs -- 2 outputs -- 2 -- -- -- -- -- -- -- 1 1 input -- -- -- -- -- -- 1 -- 1 channel 2 channels 8-bit Timer/Event Counters 5, 6 2 channels
Watch Timer 1 channel
Watchdog Timer 1 channel
18
PD780016Y, 780018Y
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal bus INTP1
Selector
TI01/P01/ INTP1
16-bit capture/ compare register (CR00)
INTTM00
Match Watch timer output
PWM pulse output control circuit
Output control circuit
TO0/P30
Selector
fXX fXX/2 fXX/22 TI00/P00/ INTP0 Edge detector
16-bit timer register (TM0) Clear Match Selector INTTM01 INTP0 16-bit capture/ compare register (CR01)
Internal bus
Figure 5-3. 8-Bit Timer/Event Counter 1, 2 Block Diagram
Internal bus
INTTM1 8-bit compare register (CR10)
Selector
8-bit compare register (CR20)
Match Match fXX/2fXX/29 fXX/211 TI1/P33
Output control circuit
TO2/P32 INTTM2
Selector
Selector
8-bit timer register 1 (TM1) Clear
8-bit timer register 2 (TM2) Clear
Selector
fXX/2fXX/29 fXX/211 TI2/P34
Selector
Output control circuit Internal bus
TO1/P31
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PD780016Y, 780018Y
Figure 5-4. 8-Bit Timer/Event Counter 5, 6 Block Diagram
Internal bus
8-bit compare register (CRn0)
Match
INTTMn TO5/P100/TI5, TO6/P101/TI6
Selector
fXX - fXX/29 fXX/211 TI5/P100/TO5, TI6/P101/TO6
8-bit timer register n (TMn)
OVF
Output control circuit
Clear
Internal bus
n = 5, 6
20
PD780016Y, 780018Y
Figure 5-5. Watch Timer Block Diagram
Selector
fW
Prescaler
Selector
fXX/27 fXT
Selector
5-bit counter
fW 214 INTWT
fW 24
fW 25
fW 26
fW 27
fW 28
fW 29 Selector
fW 213
INTTM3
To 16-bit timer/ event counter
Figure 5-6. Watchdog Timer Block Diagram
fXX 23 fXX 24 fXX 25 fXX 26
Prescaler fXX 27 fXX 28 fXX 29 fXX 211 INTWDT maskable interrupt request 8-bit counter
Control circuit
Selector
RESET INTWDT non-maskable interrupt request
21
PD780016Y, 780018Y
5.4 Clock Output Control Circuit
This circuit can output clocks of the following frequencies: * 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (at main system clock frequency of 5.0 MHz) * 32.768 kHz (at subsystem clock frequency of 32.768 kHz) Figure 5-7. Clock Output Control Circuit Block Diagram
fXX fXX/2 fXX/22 fXX/24 fXX/25 fXX/26 fXX/27 fXT
Selector
fXX/23
Synchronization circuit
Output control circuit
PCL/P35
5.5 Buzzer Output Control Circuit
This circuit can output clocks of the following frequencies that can be used for driving buzzers: * 2.4 kHz/4.9 kHz/9.8 kHz (at main system clock frequency of 5.0 MHz) Figure 5-8. Buzzer Output Control Circuit Block Diagram
Selector
fXX/29 fXX/210 fXX/211
Output control circuit
BUZ/P36
22
PD780016Y, 780018Y
5.6 A/D Converter
The A/D converter consists of eight 8-bit resolution channels. A/D conversion can be started by the following two methods: * Hardware starting * Software starting Figure 5-9. A/D Converter Block Diagram
Series resistor string ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 AVSS Successive approximation register (SAR) Sample & hold circuit AVREF
Selector
Voltage comparator
AVSS
INTP3/P03
Edge detector
Control circuit
Tap selector
INTAD INTP3
A/D conversion result register (ADCR)
Internal bus
23
PD780016Y, 780018Y
5.7 Serial Interfaces
There are the following three on-chip serial interface channels synchronous with the clock: * Serial interface channel 1 * Serial interface channel 4 * Serial interface channel 5 Table 5-3. Types and Functions of Serial Interfaces
Function 3-wire serial I/O mode (Starting bit MSB/LSB switching possible) 3-wire serial I/O mode with automatic data transmit/ /receive function 3-wire serial I/O mode with automatic data transmit/ receive function I2C bus mode (Starting bit MSB/LSB switching possible) -- (Starting bit MSB/LSB switching possible) -- Serial Interface Channel 1 Serial Interface Channel 4 Serial Interface Channel 5 --
-- (Starting bit MSB/LSB switching possible)
--
--
--
(MSB first)
Figure 5-10. Serial Interface Channel 1 Block Diagram
Internal bus
Automatic data transmit/ receive address pointer (ADTP)
Buffer RAM
Automatic data transmit/receive interval specification register (ADTI)
SI1/P20
Serial I/O shift register 1 (SIO1)
Match
SO1/P21 5-bit counter STB/P23 Handshake control circuit
BUSY/P24
SCK1/P22
Serial clock counter
Interrupt request signal generator
INTCSI1
Serial clock control circuit
Selector
fXX/22--fXX/28 TO2
24
PD780016Y, 780018Y
Figure 5-11. Serial Interface Channel 4 Block Diagram
Internal bus
Selector
SI4A/P90 SI4B/P93 SI4C/P110 SO4A/P91 SO4B/P94 SO4C/P111 SCK4A/P92 SCK4B/P95 SCK4C/P112
Serial I/O shift register 4 (SIO4)
Selector
Selector
Serial clock counter
Interrupt request signal generator
INTCSI4
Serial clock control circuit
Selector
fXX/22-fXX/28 TO2
Figure 5-12. Serial Interface Channel 5 Block Diagram
Internal bus
Slave address register 5 (SVA5) Clear Match signal P116/SDA Serial I/O shift register 5 (SIO5) Set Output latch
I2C bus interface control register (IICC)
I2C bus interface status register (IICS)
CL0 Data retention time correction circuit Wake-up control circuit
N-ch open-drain output
P116 output latch Acknowledge detection circuit Start condition detection circuit Stop condition detection circuit Acknowledge output circuit
P117/SCL
Serial clock counter Serial clock control circuit Serial clock wait control circuit Prescaler
Interrupt request signal generation circuit
INTIIC
N-ch open-drain output
P117 output latch
I2C bus interface clock select register (IICCL)
Internal bus
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PD780016Y, 780018Y
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6.1 Interrupt Functions
A total of 21 interrupt functions are provided, divided into the following three types. * Non-maskable : 1 * Maskable * Software : 19 :1 Table 6-1. List of Interrupt Factors
Interrupt Type Nonmaskable Maskable DefaultNote 1 Priority -- Name INTWDT Interrupt Factor Trigger Overflow of watchdog timer (When the watchdog timer mode 1 is selected) Overflow of watchdog timer (When the interval timer mode is selected) Pin input edge detection External 0006H 0008H 000AH 000CH 000EH 0010H 0012H Completion of serial interface channel 1 transfer Reference interval signal from watch timer Generation of matching signal of 16-bit timer register and capture/compare register (CR00) 11 INTTM01 Generation of matching signal of 16-bit timer register and capture/compare register (CR01) Generation of matching signal of 8-bit timer/event counter 1 Generation of matching signal of 8-bit timer/event counter 2 Completion of A/D conversion Generation of matching signal of 8-bit timer/event counter 5 Generation of matching signal of 8-bit timer/event counter 6 Completion of serial interface channel 4 transfer Completion of serial interface channel 5 transfer Execution of BRK instruction -- 0022H Internal 0016H 001EH 0020H (B) Internal/ External Internal Vector Table BasicNote 2 Address Structure Type 0004H (A)
0
INTWDT
(B)
1 2 3 4 5 6 7 8 9 10
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI1 INTTM3 INTTM00
(C) (D)
12
INTTM1
0024H
13
INTTM2
0026H
14 15
INTAD INTTM5
0028H 002AH
16
INTTM6
002CH
17 18 Software --
INTCSI4 INTIIC BRK
002EH 0030H 003EH (E)
Notes 1. Default priority is the priority order when several maskable interruptions are generated at the same time. 0 is the highest order and 18 is the lowest order. 2. Basic structure types (A) to (E) correspond to (A) to (E) in Figure 6-1.
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PD780016Y, 780018Y
Figure 6-1. Interrupt Function Basic Configuration (1/2) (A) Internal non-maskable interrupt
Internal bus
Interrupt request
Priority control circuit
Vector table address generator Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
IF
Priority control circuit
Vector table address generator Standby release signal
(C) External maskable interrupt (INTP0)
Internal bus
Sampling clock select register (SCS)
External interrupt mode register (INTM0)
MK
IE
PR
ISP
Interrupt request
Sampling clock
Edge detector
IF
Priority control circuit
Vector table address generator Standby release signal
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PD780016Y, 780018Y
Figure 6-1. Interrupt Function Basic Configuration (2/2) (D) External maskable interrupt (except INTP0)
Internal bus
External interrupt mode register (INTM0, INTM1)
MK
IE
PR
ISP
Interrupt request
Edge detector
IF
Priority control circuit
Vector table address generator Standby release signal
(E) Software interrupt
Internal bus
Interrupt request
Priority control circuit
Vector table address generator
IF
:
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
E : ISP : MK : PR :
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PD780016Y, 780018Y
6.2 Test Functions
Table 6-2 shows the two test functions available. Table 6-2. Test Input Factors
Test Input Factor Name INTWT INTPT4 Trigger Overflow of watch timer Detection of falling edge of port 4 Internal/ External Internal External
Figure 6-2. Basic Configuration of Test Function
Internal bus
MK
Test input signal
IF
Standby release signal
IF MK
: :
Test input flag Test mask flag
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PD780016Y, 780018Y
7. EXTERNAL DEVICE EXPANSION FUNCTIONS
The external device expansion functions connect external devices to areas other than the internal ROM, RAM and SFR. External devices connection uses ports 4 to 6 and port 8. The external device expansion function has the following two modes:
*
Separate bus mode
: External devices are connected by using an independent address bus and data bus. Because an external latch circuit is not necessary, this mode is effective for reducing the number of components and the mounting area on a printed wiring board.
*
Multiplexed bus mode
: External devices are connected by using a time-division multiplexed address/data bus. This mode is useful for reducing the number of ports used when external devices are connected.
8. STANDBY FUNCTION
The standby function intends to reduce current consumption. It has the following three modes:
*
HALT mode
: In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode.
* *
Main STOP mode : In this mode, oscillation of the main system clock is stopped. The power consumption can be reduced because the whole internal circuit is stopped. Sub-STOP mode : In this mode, oscillation of the subsystem clock is stopped. The whole operation is stopped and the power is consumed very little. Figure 8-1. Standby Function
CSS = 1 Main system clock operation CSS = 0 STOP instruction Interrupt request HALT mode (Supply of clock to CPU is stopped although clock is generated.) HALT instruction Reset HALT instruction STOP instructon Interrupt request Subsystem clock operationNote
Interrupt request
STOP mode (Oscillation of the main system clock is stopped.)
Sub-STOP mode (Oscillation of the main system clock and subsystem clock is stopped.)
HALT mode (Supply of clock to CPU is stopped although clock is generated.)
Note
Note
Current consumption is reduced by shutting off the main system clock. If the CPU is operating on subsystemclock, shut off the main system clock by setting MCC. You cannot use a STOP instruction in HALT mode.
Cautions 1. The main stop mode can be used only when the main system clock is being operated. (The oscillation of the subsystem clock cannot be stopped.) 2. When switching on the main system clock again after the subsystem clock has been used with the main system clock stopped, be sure to provide enough time for the generation to be stable with the program first.
30
PD780016Y, 780018Y
9. RESET FUNCTION
There are the following two reset methods. * External reset input by RESET pin * Internal reset by watchdog timer inadvertent program loop time detection
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PD780016Y, 780018Y
10. INSTRUCTION SET
(1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand #byte 1st Operand A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP DBNZ MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV DBNZ INC DEC MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP A rNote sfr saddr !addr16 PSW [DE] [HL] [HL + byte] [HL + B] $addr16 [HL + C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
1
None
ROR ROL RORC ROLC
r
MOV
INC DEC
B, C sfr saddr
!addr16 PSW [DE] [HL] [HL + byte] [HL + B] [HL + C] X C MOV
MOV MOV MOV MOV MOV ROR4 ROL4 PUSH POP
MULU DIVUW
Note
Except r = A
32
PD780016Y, 780018Y
(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand 1st Operand AX #word ADDW SUBW CMPW MOVW MOVW MOVW MOVWNote MOVW MOVW MOVW MOVW MOVW AX rpNote MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW SP MOVW None
rp sfrp saddrp !addr16 SP
INCW, DECW PUSH, POP
Note
Only when rp = BC, DE, HL
(3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand 1st Operand A.bit A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY MOV1 $addr16 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
(4) Call instructions/Branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand 1st Operand Basic instruction BR AX !addr16 CALL BR Compound instruction !addr11 CALLF [addr5] CALLT $addr16 BR, BC BNC BZ, BNZ BT, BF BTCLR DBNZ
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
33
PD780016Y, 780018Y
11. PACKAGE DRAWINGS
100 PIN PLASTIC QFP (14 x 20)
A B
80 81
51 50
detail of lead end
D
C
S
100 1
31 30
F
G
H
IM
J K
P
N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S
L P100GF-65-3BA1-2 MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 0.8 0.6 0.30 0.10 0.15 0.65 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.031 0.024 0.012+0.004 -0.005 0.006 0.026 (T.P.) 0.071+0.008 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
34
M
55
Q
PD780016Y, 780018Y
APPENDIX A. DEVELOPMENT TOOLS
The following tools are available for system development using the PD780016Y and 780018Y. Language Processing Software
RA78K/0Notes 1, 2, 3, 4 CC78K/0Notes 1, 2, 3, 4 DF780018Notes 1, 2, 3, 4, 8 CC78K/0-LNotes 1, 2, 3, 4 Assembler package used in common for the 78K/0 series C compiler package used in common for the 78K/0 series Device file used in common for the PD780018 subseries C compiler library source file used in common for the 78K/0 series
PROM Writing Tools
PG-1500 PA-78P0018GF
Note 8 Note 8
PROM programmer Programmer adapter connected to the PG-1500
PA-78P0018KL-T
PG-1500 controllerNotes 1, 2
Control program for the PG-1500
Debugging Tools
IE-78000-R IE-78000-R-ANote 8 IE-78000-R-BK IE-780018-R-EMNote 8 EP-78064GF-R EV-9200GF-100 In-circuit emulator used in common for the 78K/0 series In-circuit emulator used in common for the 78K/0 series (for integrated debugger) Break board used in common for the 78K/0 series Emulation board used in common for the PD780018 subseries Emulation probe used in common for the PD78064 subseries Socket mounted on the target system board prepared for 100-pin plastic QFP (GF-3BA type) EV-9900 SM78K0Notes 5, 6, 7 ID78K0Notes 4, 5, 6, 7, 8 SD78K/0Notes 1, 2 DF780018Notes 1, 2, 4, 5, 6, 7, 8 Tool used for removing the PD78P0018YKL-T from the EV-9200GF-100. System simulator used in common for the 78K/0 series Integrated debugger for IE-78000-R-A Screen debugger for the IE-78000-R Device file used in common for the PD780018 subseries
35
PD780016Y, 780018Y
Real-Time OS
RX78K/0Notes 1, 2, 3, 4 MX78K0
Notes 1, 2, 3, 4
Real-time OS used for the 78K/0 series OS used for the 78K/0 series
Fuzzy Inference Development Support System
FE9000Note 1/FE9200Note 6 FT9080Note 1/FT9085Note 2 FI78K0Notes 1, 2 FD78K0Notes 1, 2 Fuzzy knowledge data creating tool Translator Fuzzy inference module Fuzzy inference debugger
Notes 1. Based on PC-9800 series (MS-DOSTM) 2. Based on IBM PC/ATTM and compatible machines (PC DOSTM /IBM DOSTM/MS-DOS) 3. Based on HP9000 series 300TM (HP-UXTM) 4. Based on HP9000 series 700TM (HP-UX), SPARCstationTM (SunOSTM), and EWS-4800 series (EWS-UX/ V) 5. Based on PC-9800 series (MS-DOS + WindowsTM) 6. Based on IBM PC/AT and compatible machines (PC DOS/IBM DOS/MS DOS + Windows) 7. Based on NEWTM (NEWS-OSTM) 8. Under development Remarks 1. For development tools supplied by third-party manufacturers, refer to 78K/0 Series Selection Guide (U11126E). 2. Use the RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 in combination with the DF780018.
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PD780016Y, 780018Y
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document Document No. Japanese English To be prepared This document To be prepared IEU-1372 -- -- --
PD780018Y, 780018Y Subseries User's Manual PD780016Y, 780018Y Preliminary Product Information PD78P0018Y Preliminary Product Information
78K/0 Series User's Manual-Instruction 78K/0 Series Instruction Table 78K/0 Series Instruction Set
U11754J U11810J U11603J IEU-849 U10903J U10904J To be prepared
PD780018Y Subseries Special-Function Register Table
Documents on Development Tools (User's Manuals)
Document RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler Operation Language CC78K0 C Compiler Operation Language CC78K/0 C Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Base PG-1500 Controller IBM PC Series (PC-DOS) Base IE-78000-R IE-78000-R-A IE-78000-R-BK IE-780018-R-EM EP-78064 SM78K0 System Simulator Windows Base SM78K Series System Simulator Reference External component user open interface specification ID78K0 Integrated Debugger EWS Base ID78K0 Integrated Debugger PC Base ID78K0 Integrated Debugger Windows Base SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Base SD78K/0 Screen Debugger IBM PC/AT (PC DOS) Base Reference Reference Guide Introduction Reference Introduction Reference U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J -- -- -- -- -- EEU-1414 EEU-1413 Programing Know-how Document No. Japanese EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 U11517J U11518J EEA-618 EEU-777 EEU-651 EEU-704 EEU-5008 EEU-810 U10057J EEU-867 U11838J EEU-934 U10181J U10092J English EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 -- -- EEA-1208 -- EEU-1335 EEU-1291 U10540E U11376E U10057E EEU-1427 To be prepared EEU-1469 U10181E U10092E
Caution The above documents are subject to change without notice. Be sure to use the latest documents for design or for any other similar purpose.
37
PD780016Y, 780018Y
Documents on Embeded Software (User's Manuals)
Document Basic 78K/0 Series Real-time OS Installation Technical 78K/0 Series OS MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-858 EEU-921 EEU-1441 EEU-1458 Fundamental Document No. Japanese U11537J U11536J U11538J EEU-5010 EEU-829 EEU-862 English -- -- -- -- EEU-1438 EEU-1444
Other Documents
Document IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Semiconductor Device Quality Assurance Guide Microcontroller-Related Product Guide - Third Party Products - Document No. Japanese English
C10943X C10535J C11531J U10983J MEM-539 MEI-603 U11416J C10535E C11531E U10983E -- MEI-1202 --
Caution The above documents are subject to change without notice. Be sure to use the latest documents for design or for any other similar purpose.
38
PD780016Y, 780018Y
[MEMO]
39
PD780016Y, 780018Y
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
40
PD780016Y, 780018Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
41
PD780016Y, 780018Y
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M4 96.5

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